1. Field of the Invention
The present invention relates generally to a fabrication method of packaging structure, and more particularly, to a fabrication method of quad flat non-leaded (QFN) semiconductor package and a fabrication method thereof.
2. Description of Related Art
Conventionally, a lead frame is used as a chip carrier for carrying a chip so as to form a semiconductor package. The lead frame mainly comprises a die pad and a plurality of leads disposed around the periphery of the die pad. The chip is adhered to the die pad and electrically connected to the leads through a plurality of bonding wires. The chip, the die pad, the bonding wires and the inner sections of the leads are then encapsulated by a packaging resin so as to form a semiconductor package with a lead frame.
Currently, the development of packaging structures with high integration and high density has become the primary goal of the industry. Carriers used for chip scale packages generally comprise lead frames, flexible substrates, rigid substrates and so on. Therein, the lead frames are most widely used due to their low cost and ease of processing. For example, a QFN package is a lead frame based chip scale package, which is characterized in that the leads thereof do not extend out from the package sides, thus reducing the overall package size.
FIG. 4A is a cross-sectional view of a QFN package using a lead frame as a chip carrier as disclosed by U.S. Pat. Nos. 6,143,981, 6,130,115 and 6,198,171. Referring to FIG. 4A, a chip 42 is disposed on a lead frame 40 having leads 41 and is electrically connected to the leads 41 through a plurality of bonding wires 43, and an encapsulant 44 is formed to encasuplate the lead frame 40, the chip 42 and the bonding wires 43 while exposing the bottom surfaces of the leads 41. As such, by disposing a solder material (not shown) on the exposed surfaces of the leads 41, the packaging structure can be electrically connected to an external device such as a printed circuit board through the solder material.
However, the above-described lead frame type structure has quite limited I/O count and therefore cannot meet the requirement of high-level products. Further, the leads of the lead frame may fall off after a singulation process of the packaging structure. Furthermore, as shown in FIG. 4B, since the exposed surfaces of the leads 41 are flush with the encapsulant 44, when solder balls are mounted to the leads 41 for electrically connecting an external printed circuit board, a solder bridge can easily occur between adjacent solder balls so as to form a bridge or short circuit between the leads 41, thus resulting in poor electrical connection of the packaging structure.
In addition, a lead frame can be formed by etching a copper foil substrate so as to increase the number of leads, thereby increasing the I/O count. However, such an etching process is quite complicated and time-consuming. Further, when an encapsulant is filled in the above-described structures, the encapsulant may overflow to the exposed surfaces of the leads, thus adversely affecting the mounting of solder balls and the electrical connection of the solder balls and leads. Furthermore, the lead frame formed by etching a copper foil substrate generally has a separated and incomplete structure, which often causes loose soldering to occur in an ultrasonic soldering process.
Therefore, it is imperative to provide overcome the above drawbacks of the prior art.